Direct-to-Chip Cooling in Data Centers - and Learnings from Semiconductor

AI workloads, and the increasingly dense chips that support them, are forcing a step-change in data center cooling. Air cooling is effectively obsolete for data centers supporting the current generation of high-performance computing, with direct-to-chip cooling emerging as the dominant alternative.

By global capacity served, direct liquid cooling is expected to grow from around 5% currently to 28% by 2030, according to GWI.

With this shift, data centers are rethinking water use. Cooling water, which was once low-concern, is now approaching semiconductor or pharmaceutical grade process water, where sensitivity and vastly reduced tolerances introduce unfamiliar approaches to fluid management.

There are five key challenges associated with water for direct-to-chip cooling, all with engineering precedents in the semiconductor industry.

1. Commissioning

While chiller loops and their startup processes are familiar ground for data centers, the pre-operational cleaning of direct-to-chip systems adds a new layer of complexity to commissioning. Where a traditional chiller loop might involve a single large circuit, a direct-to-chip installation serving high-density racks can involve 20 to 30 discrete technology cooling loops, each requiring individual chemical cleaning, passivation, and rinsing.

Data center developments are starting to explore modular and pre-commissioned cooling loop assemblies, mirroring the semiconductor industry’s approach to deploying clean systems at scale. While polymer -based piping loops – the standard for fab UPW systems – also promises streamlined commissioning for data centres, they are yet to find their feet in the sector.

2. Fluid cleanliness and filtration

While treatment approaches for direct-to-chip loops are similar to open-loop facility cooling systems – a mixture of chemical dosing and filtration – low thresholds for system fouling mean that treatment technology must be consistent and reliable.

With fluid recirculating between coolant distribution unit (CDU) loops and servers, both chip designers and cooling OEMs are issuing guidance on filtration sizing to limit fouling of the cold-plate microchannels. NVIDIA’s current guidance specifies 25µm, but some operators are already pushing filtration down to 0.5µm, in anticipation of higher-performance chips in the future.

Actual liability and operational responsibility of these loops is less clear cut, however. Chip designers, CDU manufacturers, and water or fluid treatment providers are all vying to influence end-user choices, creating gaps that can trickle down to engineering concerns.

3. Monitoring

Corrosion monitoring in closed systems has typically been carried out with copper coupons or strips left in loops to track material loss. While they give reliable average corrosion rates, they are unable to track the shorter term changes that can very quickly cause performance drops in these tightly specified systems.

Continuous tracking of glycol content, pH, conductivity, turbidity, and differential pressure offers a far more comprehensive view on system operation. An abstract from Ecolab planned for UltraFacility 2026, drawing on field data from hundreds of deployed monitoring units, points toward integrating online monitoring directly into CDU control logic. The harmonization of water and fluid treatment with cooling equipment is a clear sign of where the industry is headed, both in terms of commercial consolidation and operational centralisation.

4. Materials compatibility

Unlike in the semiconductor sector, materials selection in data centers is often a secondary concern. As such, new builds are increasingly rubbing up against the limitations associated with the materials of choice for direct-to-chip systems.

Stainless steel piping releases ions at the high recirculation rates and small loop volumes typical of DTC installations. Copper cold plates are well-suited to these applications from a thermal standpoint, but corrode in overly pure water. Polymer alternatives reduce ion leaching but do not eliminate the need for inhibitor dosing where copper heat exchangers and cold plates remain in the wetted circuit.

5. The shift toward pure water

Most current direct-to-chip deployments use a mixture of deionized water and propylene glycol as the coolant. Glycol offers biostatic safety and passive corrosion inhibition, but it can also limit heat transfer capacity by up to 7% and push up required pumping pressure by up to 35% due to greater viscosity.

As rack densities climb, and some direct-to-chip deployments hit thermal limits, these efficiency penalties will have an increasingly material impact on design choices, and will continue to push operators to consider pure water loops. With this increase in system sensitivity comes ramped up treatment and monitoring requirements, further pushing direct-to-chip loops toward the kind of process water management seen in semiconductor fabs.

These engineering problems are being seen across the global data centre buildout, and the abstracts accepted for UltraFacility 2026 reflect an emerging part of the supply chain working across both sectors and drawing together engineering expertise.

On Day 0 (16 September, Phoenix), a half-day workshop brings together data center operators, semiconductor engineers, and cooling specialists – the full scope of data center cooling – for a discussion on the strategic overlap between the two sectors, structured technical exchange on cooling, and a rich networking opportunity.

The session is invite-only; those interested can enquire at team@ultrafacility.io.