Carollo Engineers

Microelectronics UPW Technical Director for Evoqua Water Technologies, LLC. Responsible for process development, optimization, troubleshooting and technical support of high purity water systems within the semiconductor, nanotechnology and solar markets. Also responsible for operating and maintaining an E-1.2 UPW system in the Evoqua Microelectronics Technology Suite. Has been with Evoqua (starting with IWT) for over 37 years in various roles responsible for developing, growing and supporting products and technologies within the Corporate and Industrial segments. These roles include; Product Manager, Process Development Manager and Applications Engineering Manager. Bachelor of Science in Chemical Engineering, with emphasis on high-energy physics, from the University of Wisconsin, Madison, and located at the Evoqua office in Rockford, Illinois. Authored and co-authored several papers on topics including nanofiltration, reverse osmosis, ultrafiltration, advanced oxidation and particle removal for the semiconductor industry.

Xylem

Tina is a civil engineer working for Kokosing, a self-performing heavy industrial contractor in the Midwest and Mid-Atlantic. She holds a BS in CE from Case Western Reserve University and a MS in CE from Cleveland State University. Tina is a licensed PE in IL, IN, MI, PA, OH.

Kokosing Industrial

Dr. Rushikesh (Rushi) Matkar is the Pathfinding Technologist for Water purification at Intel’s R&D Center in Hillsboro, OR and a corporate owner for the leadership roadmap of Intel's water management group. Responsible for driving solutions towards the success of Intel's high volume manufacturing roadmap. He is passionate about high purity delivery of utilities, IOT and advanced manufacturing. Between Academia and Industry, Rushi has extensive experience in bringing new IP to Market. Recently, Rushi successfully led the program to introduce EUV Lithography as a patterning solution for fabrication at Globalfoundries. He has served multiple roles within the leading nodes in technology management, operations and engineering management to help multiple technology nodes meet mass-market benefits.

Ovivo

Latif joined Intel in 2005 as Microcontamination Engineer for the startup of 45nm process at Fab-32 in Arizona. He has been involved in four more process transfers to Arizona, including the latest 10nm startup. He is technical expert in Microcontamination, including AMC’s, with over 25 years of experience in environmental, semiconductor testing, AMC’s and other Microcontamination problem solving. Prior to joining Intel, Latif worked as a Research Scientist at Balazs Analytical and as a Technical Support Manager at ChemTrace. Latif has participated in collaborative efforts with many chemical and equipment manufacturing companies and organizations including, Sematech, Factory Mutual Research Corporation, in development of criteria for approval of materials suitable for use in semiconductor fabs.

Intel

Please see my LinkedIn profile: https://www.linkedin.com/in/sergei-shatsman/

FTD Solutions

Bernie Zerfas is a former facilities engineer at GLOBALFOUNDRIES. He has more than 30 years’ experience in the semiconductor industry with a primary focus on UPW and deionized water systems. Although his initial formal training was in chemistry and chemical engineering, he has had a wide variety of formal and informal educational experiences in a variety of technical disciplines. Mr. Zerfas is also an active member of the UPW sub-group of the ITRS; a recent area of focus has been organic and particulate contamination. His current other areas of responsibility include a spectrum of pollution control systems.

Dr. Altun is the co-founder and CEO of UNISERS AG, an ETH Zurich spinoff from Switzerland. UNISERS has been developing a wafer defect inspection and review tool with a sub-10nm detection limit. Dr. Altun has 15-year experience in nanotechnology and optical sensing. Prior to his position at UNISERS AG, he did a Ph.D. at ETH Zurich. He worked at Lawrence Livermore National Laboratories (2011-2014) and Korean Institute of Machinery and Materials (2005-2010). He had his B.Sc. degree from METU (Middle East Tech. Univ.), Turkey and M.Sc. degree at KAIST (Korea Advanced Institute of Science and Technology).

UNISERS

Dominic is the Intel Director of Construction responsible for managing Intel’s latest leading edge Wafer FAB construction Program at Intel’s Ocotillo Campus Phoenix AZ. This program is part of Intel’s $20b investment on the campus.


Dominic has 35 years’ experience in EPCC project delivery. 16 years working with EPCC firms Costain, Jacobs, Fluor, DPS and 20 years within Intel.


Dominic holds a BSc in Construction Technology and an MSc in Project management.




Senior Process Chemical Engineer with 30+ years of experience working in Facilities Operation Engineering and Design within the semiconductor manufacturing industry. He is a Subject Matter Expert in chemicals, chemical systems, and application for semiconductor manufacturing, pollution abatement, water and wastewater treatment and supporting HazWaste systems and operation.

Micron

Dan’s almost three decades of experience as a facilities engineering manager, process engineer, design engineer, construction project manager and tool hookup design in the advanced technologies and semiconductor manufacturing industry has led to innovative solutions in his work. His innovations have resulted in industry-changing quality and cost savings breakthroughs, including defect reduction and innovative water reclaim and re-use systems. Dan is well established in the semiconductor industry as an Ultra-pure Water, UHP Chemical and Wastewater expert as shown in his leadership of industry roadmap and collaboration teams. He is certified by ASQ as a six sigma black belt. His roles include Co-Chair of International Roadmap for Device and Systems (IRDS) Yield Enhancement (YE) team, Co-Chair UPW SEMI Standards team, and UP Micro Conference Strategy Team. In addition to many industry publications, Dan also holds a patent for Reduction of Charging Induced Damage in Photolithography Wet Process.

Samsung Austin Semiconductor

Kevin Wolfe is an environmental engineer working within the Global Environmental department at Intel Corporation. He has been working at Intel for 21 years in many environmental health and safety capacities, and currently leads the PFAS working group internal to Intel, and helps to project manage the SIA Semiconductor PFAS Consortium that intends to work towards developing the technical information that will be required to effectively engage with PFAS regulatory restriction efforts.

Alain is a Global Technical Lead and Senior Application Specialist TSI Incorporated, based in Aachen, Germany. With over 30 years in contamination control, cleanroom monitoring, and precision instrumentation, he supports global teams and customers in implementing advanced environmental monitoring strategies across pharmaceutical, semiconductor, and life science industries, including expertise in Facility Monitoring Systems (FMS) Software for real-time data management and compliance.


Before TSI, Alain held senior engineering and project management roles, leading complex cleanroom installations, particle monitoring systems, and facility validation projects. Known for blending technical expertise with practical application, he helps organizations achieve the highest standards of contamination control and regulatory compliance worldwide.


Alain is an active member of ISPE, PDA, IEEE, IRDS, and the UltraFacility community, contributing to industry best practices and innovation in contamination control.

Jas Cheong

More UltraFacility members